Design Verification Engineer
- Posted a month ago
- Be among the first 10 applicants
Job Description
Experience: 5 Years
Location: Bangalore/Hyderabad
Education: B.E/B.Tech in ECE/EEE or M.E/M.Tech in VLSI/Electronics
Roles and Responsibilities
- Verilog, System verilog, UVM
- VHDL, UVVM
- Simulator exposure with VCS, Questa, Xcelium
- Proficient in simulation and HW languages
- Should be able to interpret various LRMs and comply with semantics and testcase creation.
Share the profiles to [Confidential Information].
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
About Company
Skills:
C, C++, Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, Post-silicon debugging, RTL design and verification flows, Simulation Tools, JTAG protocols, Digital Design, Assembly language programming
Skills:
Computer Architecture, C, Assembly Language, Vcs, Perl, Verilog, Python, System Verilog, Computer Engineering, Raven, UVM methodology, ACK, Microelectronics, Questa, Electrical Engineering
Skills:
Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation
Skills:
Jtag, C, Verilog, System Verilog, Uvm, SOC RTL Design Verification
Skills:
Unix, Bug Tracking, Makefile, Shell, Configuration Management, PERL, Python, Verification dashboarding tools, Random stimulus, ARM CPU, PCI Express, Uvm, Functional coverage, systemverilog, AMBA bus protocols, Ethernet bus protocols