C, C++, Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, Post-silicon debugging, RTL design and verification flows, Simulation Tools, JTAG protocols, Digital Design, Assembly language programming

Jtag, C, Verilog, System Verilog, Uvm, SOC RTL Design Verification

Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation

Computer Architecture, C, Assembly Language, Vcs, Perl, Verilog, Python, System Verilog, Computer Engineering, Raven, UVM methodology, ACK, Microelectronics, Questa, Electrical Engineering

Unix, Bug Tracking, Makefile, Shell, Configuration Management, PERL, Python, Verification dashboarding tools, Random stimulus, ARM CPU, PCI Express, Uvm, Functional coverage, systemverilog, AMBA bus protocols, Ethernet bus protocols

C, Uart, Spi, Pcie, I2c, Axi, APB, AHB, simulation and debugging tools from Synopsys, Cadence, Siemens EDA, Uvm, systemverilog

Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog

Usb, Fpga, Perl, Pcie, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, test bench infrastructure, transaction level modeling, AXI4

SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification

C, Perl, Computer Architecture, Ruby, Python, Assembly start up code, Makefiles, Stimulus generation, Uvm, Testbenches, Pre-silicon verification, Formal verification methods, Linker scripts, Post-silicon FPGA validation