Lead Design Engineer
Lead Design Engineer
CADENCE- Posted 17 hours ago
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Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The Lead Analog Design Engineer will take a Key role on the Analog and Mixed signal design team as part of a Die to Die Product Development Team.
Job Responsibilities
Cadence tool experience is desirable and design experience at >10Gbps and inLab test experience as part of silicon evaluation is advantageous
We're doing work that matters. Help us solve what others can't.
The Lead Analog Design Engineer will take a Key role on the Analog and Mixed signal design team as part of a Die to Die Product Development Team.
Job Responsibilities
- Design of High Speed D2D and SERDES products at industry standard data rates up on leading edge technology nodes (e.g. 3nm FinFET CMOS)
- Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications
- Work closely with Layout Design Engineers to design IC circuit blocks and PMA sections
- Work with Technical Team Leads in the areas of circuit design and SERDES architectures
- Work with global teams (US, west coast and east coast), which work in different time-zones
- BEng, MEng, PhD or equivalent.
- Candidate's background should include a minimum of 5 years of CMOS design experience, preferably in the area of CMOS SERDES or high-speed I/O IC design
- Should have a good understanding of jitter and signal equalization techniques
- Design experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators
- Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment
- Position requires proficiency in using CAD tools for circuit simulation, layout and physical verification
Cadence tool experience is desirable and design experience at >10Gbps and in
More Info
Key Skills
Phase Interpolator
CAD tools for circuit simulation
Cadence tool experience
CMOS design
Bias and Bandgap Voltage Regulators
jitter and signal equalization techniques
High Speed Clock Distribution
Low jitter PLL
layout and physical verification
About Company
Skills:
Matlab, Worst case identification, Monte Carlo analysis, Physical layout management, AMs, Analog Circuit Design, Spectre, Cadence tool set, Top level simulation, Simplis, Post layout parasitic extraction, Schematic generation and simulation, Top level verification, Knowledge of device physics and process technologies, Block level modelling, Simulation data analysis, IC transistor level implementation, IC system partitioning and architectural tradeoff analysis, Power IC design, Signal grounding and routing tradeoffs, Die area optimization
Skills:
variation analysis , monte carlo , Python, Perl, Tcl, FineSim, IR drop, yield analysis, ECC redundancy and repair strategies, multi-Vt, circuit simulation tools, scripting knowledge, CMOS analog digital circuit design principles, Pvt, low-power memory design techniques, memory compiler design and automation, ISO 26262 Safety compliance, silicon debug, power gating, EM checks, XA, FastSPICE, Spectre, Hspice, Memory Characterization, multi-Vdd
Skills:
PCS, Perl, Python, Tcl, reusable verification infrastructure, PHY link protocols, UVM environment development, high-speed interface verification, Uvm, systemverilog, Ethernet MAC, functional coverage closure, Ethernet protocol compliance verification, packet processing, complex protocol debug, SerDes controller validation, SVA, error handling
Skills:
Pll, compensation techniques, transistor capacitor matching, transistor level circuit design, EDA Tools, analog mixed signal design, SERDES, high-speed TX, noise analysis