Design Rule Checks (DRC), Layout-versus-Schematic (LVS), Analog Circuit Design, Post-silicon debug, Custom Layout, Floor Planning, Foundry-specific design guidelines, Analog Layout Design, Device matching, Parasitic-aware layout optimization

bandgap references , static timing analysis, Verilog, PLLs, Synthesis, Clock-domain crossing CDC, Oscillators, ADCs, Low-power design fundamentals, systemverilog, Reset-domain crossing RDC, FSM design, Rtl Design, DACs, Timing Concepts, LDOs

simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, IP integration, DFT specification definition, silicon debug activities

Phase Interpolator, CAD tools for circuit simulation, Cadence tool experience, CMOS design, Bias and Bandgap Voltage Regulators, SERDES, jitter and signal equalization techniques, High Speed Clock Distribution, Low jitter PLL, layout and physical verification

Bias generators, Bandgaps, Simulation verification, Cadence Virtuoso Spectre, ADCs, SPICE-based simulations, Analog Circuit Design, Power-management ICs, DRC LVS extraction, MOSFET physics, DACs, Silicon debug support, Driver amplifiers, DC-DC converters, Post-layout verification, Sensing circuits, Gate drivers, Error amplifiers, Charge pumps, LDOs, Level shifters, Analog Layout

Dac, Digital Signal Processing, Analog Design, Sigma Delta ADC, Signal Processing

Static checks (Lint, rtl development , Power checks), Clock power domain implementations, Verilog Hdl, Synthesis timing analysis, Power management and low-power design techniques, digital hardware design, ARM System Architectures, DFT and physical implementation flows, Micro-architecture specifications, ARM-based designs, cdc, RDC, Advanced synthesis checks

Python Scripting, silicon debug, FinSim, Circuit Simulation, XA, Power gating architecture, Silicon Failures Analysis, CMOS Circuit Design, XARA, HSIM, Hspice, nWave