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Job Title: Design Engineer II
Company: Cadence
Location: Hyderabad
Job Type: Full-Time
Overview:
Cadence is seeking an experienced Foundation IP Quality Lead to drive the Product validation efforts for standard cells, IO libraries, and memory compilers across advanced nodes. This critical role ensures our IP products meet high standards in performance, manufacturability, and reliability.
Key Responsibilities:
Drive quality strategies and sign-off methodologies for Foundation IP.
Lead QA reviews, audits, and compliance for IP deliverables (Ex : Review of DRC/LVS, timing, reliability).
Analyze silicon and customer data to improve quality processes.
Collaborate with design, validation, and customer teams.
Mentor engineers and advocate for quality-first practices.
Qualifications:
B.S./M.S. in Electrical or Computer Engineering.
4+ years in semiconductor IP QA/design with strong foundation IP expertise.
Proficiency with EDA tools (Cadence, Synopsys, Mentor).
Knowledge of quality standards and silicon validation.
Preferred:
Background in advanced nodes, PDKs or memory validation.
Experience in EDA view generation and validation.
Why Cadence
Join an award-winning, collaborative culture working on cutting-edge technologies powering AI, 5G, automotive, and cloud computing.
Cadence is a health technology company helping the nation’s most patient-centric health systems deliver more consistent, proactive healthcare every day. Cadence’s remote patient intervention solution couples powerful new technology with clinical excellence, providing its patients a precise and personal level of care all outside of the four walls of the hospital.At Cadence, we aim to exceed the expectations of our patients, clinicians, and partners every day. Our team values trust and autonomy, and we empower one another to make decisions, solve problems and build something better. We give clear, candid feedback with the utmost honesty and encouragement. If you’re interested in joining us, explore opportunities at www.cadence.care.
Job ID: 149923145
Skills:
Silicon Validation, quality standards, EDA Tools, Mentor, Cadence, Synopsys
Skills:
Tcl, Jtag, Perl, chip tape out, MBIST, Analog Macro tests, timing SDF simulations, coverage improvement techniques, test mode timing constraints, block level and chip STA flows, ATPG, DFT IP integration, Fault Models, debug on ATE, Cadence Tessent tools, Scan, post-silicon bring up, test point insertion, gate level simulation, scan insertion techniques, Memory BIST generation
Skills:
Verilog, Usb, Tcl, Ethernet, Git, Ecos, C, Perforce, Python, Pcie, DDR, Xilinx Vivado, systemverilog, Cadence, static RTL checks, Synthesis, Axi, FPGA design tools, Mentor simulation suites, Intel Quartus, AMBA bus protocols, low power design techniques, Rtl Design, Lattice Diamond, STA timing closure, SoC architectures
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