Search Jobs
Search by job, company or skills
Search by job, company or skills
Job Title: Design Engineer II
Company: Cadence
Location: Hyderabad
Job Type: Full-Time
Overview:
Cadence is seeking an experienced Foundation IP Quality Lead to drive the Product validation efforts for standard cells, IO libraries, and memory compilers across advanced nodes. This critical role ensures our IP products meet high standards in performance, manufacturability, and reliability.
Key Responsibilities:
Drive quality strategies and sign-off methodologies for Foundation IP.
Lead QA reviews, audits, and compliance for IP deliverables (Ex : Review of DRC/LVS, timing, reliability).
Analyze silicon and customer data to improve quality processes.
Collaborate with design, validation, and customer teams.
Mentor engineers and advocate for quality-first practices.
Qualifications:
B.S./M.S. in Electrical or Computer Engineering.
4+ years in semiconductor IP QA/design with strong foundation IP expertise.
Proficiency with EDA tools (Cadence, Synopsys, Mentor).
Knowledge of quality standards and silicon validation.
Preferred:
Background in advanced nodes, PDKs or memory validation.
Experience in EDA view generation and validation.
Why Cadence
Join an award-winning, collaborative culture working on cutting-edge technologies powering AI, 5G, automotive, and cloud computing.
Job ID: 149952013
Skills:
Silicon Validation, Mentor, Synopsys, EDA Tools, quality standards, Cadence
Skills:
Jtag, Perl, test point insertion, MBIST, Analog Macro tests, timing SDF simulations, coverage improvement techniques, test mode timing constraints, block level and chip STA flows, ATPG, chip tape out, DFT IP integration, Fault Models, debug on ATE, Cadence Tessent tools, Scan, post-silicon bring up, gate level simulation, Memory BIST generation, scan insertion techniques
Skills:
Verilog, Usb, Tcl, Ethernet, Git, Ecos, C, Perforce, Python, Pcie, DDR, Xilinx Vivado, systemverilog, Cadence, static RTL checks, Synthesis, Axi, FPGA design tools, Mentor simulation suites, Intel Quartus, AMBA bus protocols, low power design techniques, Rtl Design, Lattice Diamond, STA timing closure, SoC architectures
We don’t charge any money for job offers
