Silicon Validation, quality standards, EDA Tools, Mentor, Cadence, Synopsys

Tcl, Jtag, Perl, chip tape out, MBIST, Analog Macro tests, timing SDF simulations, coverage improvement techniques, test mode timing constraints, block level and chip STA flows, ATPG, DFT IP integration, Fault Models, debug on ATE, Cadence Tessent tools, Scan, post-silicon bring up, test point insertion, gate level simulation, scan insertion techniques, Memory BIST generation

Verilog, Usb, Tcl, Ethernet, Git, Ecos, C, Perforce, Python, Pcie, DDR, Xilinx Vivado, systemverilog, Cadence, static RTL checks, Synthesis, Axi, FPGA design tools, Mentor simulation suites, Intel Quartus, AMBA bus protocols, low power design techniques, Rtl Design, Lattice Diamond, STA timing closure, SoC architectures