Silicon Validation, Mentor, Synopsys, EDA Tools, quality standards, Cadence

Jtag, Perl, test point insertion, MBIST, Analog Macro tests, timing SDF simulations, coverage improvement techniques, test mode timing constraints, block level and chip STA flows, ATPG, chip tape out, DFT IP integration, Fault Models, debug on ATE, Cadence Tessent tools, Scan, post-silicon bring up, gate level simulation, Memory BIST generation, scan insertion techniques

Verilog, Usb, Tcl, Ethernet, Git, Ecos, C, Perforce, Python, Pcie, DDR, Xilinx Vivado, systemverilog, Cadence, static RTL checks, Synthesis, Axi, FPGA design tools, Mentor simulation suites, Intel Quartus, AMBA bus protocols, low power design techniques, Rtl Design, Lattice Diamond, STA timing closure, SoC architectures