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Job Description:
Responsibilities:
Job ID: 148676197
Skills:
Scripting Language, Linux Operating System, Agile development processes, Verification principles, DevOps design methodologies and tools, RTL design with Verilog or VHDL
Skills:
Verilog, DDR, Test Planning, systemverilog, Uvm, Rtl Design, Functional Verification, LPDDR, HBM, Memory Subsystems, Verification Environment Development
Skills:
C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, Veloce, ASIC Design, formal verification
Skills:
System Verilog, Design Verification, Functional Verification, Environment Development, Uvm, Test Plan Generation
Skills:
SAP, Enovia, Team-Center PLM, Composites and metallic components assembly, MBD creation, CPD fibersim workbenches, Mechanical engineering fundamentals, Design Principles, Mechanical structures Design and Development, Material Fastener selection
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