CPU Design Verification - Multiple Levels

General Summary:

Qualcomm is seeking experienced Design Verification (DV) engineers to verify high-performance and low-power CPUs, focusing on power management features including boot, reset, clock gating, power gating, voltage/frequency management, limit management, and throttling.

Roles and Responsibilities:

• Develop and execute comprehensive power management verification plans, collaborating closely with CPU design and verification teams.
• Use simulation and formal verification methodologies, including writing checkers, assertions, and stimulus generation.
• Verify power intent with methodologies such as UPF (Unified Power Format).
• Work with system architects, software, and SoC teams to validate system-level use cases.
• Collaborate with emulation teams to enable verification on emulators and FPGA platforms.
• Debug and triage failures occurring in simulation, emulation, or silicon testing.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years experience, OR
• Master's degree with 3+ years experience, OR
• PhD with 2+ years experience in Hardware Engineering.
• Strong experience in power management verification (clock gating, power gating, UPF, DVFS/DCVS, throttling).
• Skilled in embedded firmware programming with assembly and C language.
• Proficient in C/C++, scripting languages, Verilog/SystemVerilog.
• Solid understanding of power management features in CPUs and CPU-based SoCs.

Preferred Qualifications:

• Good understanding of CPU architectures and microarchitectures.
• Deep knowledge of digital logic design, microprocessor debug features, DFT architecture, and microarchitecture.
• Experience with advanced verification techniques such as formal verification and assertions.
• Familiarity with DFT and structural debug methodologies including JTAG, IEEE1500, MBIST, scan dump, and memory dump.