Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience in power enhancement workflow and techniques.
- Experience with power management IPs.
Preferred qualifications:
- Experience in low power design including UPF/CPF, multi-voltage domains, power gating, and on-chip power management IP design.
- Experience in Verilog, SystemVerilog, RTL, and gate-level SPICE simulations, and statistical SPICE models.
- Experience using EDA tools like Conformal LP, Power-Artist, DC/RC, PT/PTPX, Incisive/VCS.
- Experience in post-silicon power calibrations and debug.
- Experience in design and analysis of full-chip power with an understanding of clock, reset, and power sequencing interactions.
Responsibilities:
- Drive architecture and microarchitecture development for next-generation power management controllers all the way from specification to SoC deployment.
- Develop Power optimization methods for various chassis IPs.
- Influence Power methodology for design, verification, and implementation of deep sub-micron SoCs.
- Develop innovative plans to achieve power optimization from circuit to system level.
- Influence generic power management IPs to drive clock, reset, and power controls.
