- We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to handle the challenging problems in future technologies and designs.
- We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team.
- Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world.
- We are looking for a passionate & experienced EDA Methodology Engineer to join our timing team focusing on timing methodology using IBM Einstimer, Cadence & Synopsys tools.
- In this role, you will work closely with design teams & EDA vendors to develop, implement & support robust timing methodology.
- Strong interpersonal skills are needed to coordinate deliverables and requirements from several areas within and outside of the organization.
- There are many opportunities to gain and utilize a deep understanding of future issues and provide input towards decisions affecting system development, logical and physical design as well as sophisticated methodology directions.
- Individuals who are chosen to become a part of our world-class development teams will be helping advance IBM's leadership in developing the highest performing computers and changing hardware solutions.
- Do you want to be an IBMer Come THINK with us!
Required education
Preferred education
Required technical and professional expertise
- 5-8 years of hands-on experience with Static Timing Analysis
- Hands-on experience with Cadence Tempus tool
- EDA Tool/Methodology development experience
- Thorough understanding of Static Timing Analysis. Knowledge of other VLSI domains is a plus
- Proven problem-solving skills and the ability to work in a team environment are a must
- Excellent scripting skills - TCL /Python/Shell
Preferred technical and professional experience
- Experience with Synopsys Primetime tool
- Experience with signoff timing in large scale SoC projects
- VLSI knowledge, Machine Learning/AI
