ASIC RTL Design Engineer
ASIC RTL Design Engineer
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Job Description
About This Job
LeadSoc Technologies Pvt Ltd
Location: Bengaluru, Karnataka, India
Work Mode: On-site
Industry: Semiconductor Manufacturing,Engineering Services,IT Services and IT Consulting
Job Description
ASIC RTL Design Engineer
Location: Bengaluru, India
Experience: 5–10 Years
Role Summary
We are looking for a highly skilled ASIC RTL Design Engineer to design and develop high-performance PCI Express (PCIe) IPs and SoC components. The ideal candidate will have strong expertise in microarchitecture definition, RTL design, and implementation of high-speed digital logic for next-generation semiconductor products.
Key Responsibilities
Design and implement RTL for PCI Express (PCIe) controllers, subsystems, and high-speed digital IPs.Translate architecture specifications into efficient microarchitecture and high-quality RTL.Develop scalable, high-performance, and low-power digital designs using Verilog/SystemVerilog.Perform functional analysis, logic optimization, lint, CDC, and synthesis-ready RTL development.Collaborate with Architecture, Verification, Physical Design, DFT, and Firmware teams throughout the development cycle.Support design reviews, debug functional issues, and resolve silicon bring-up challenges.Drive design quality through coding guidelines, documentation, and best engineering practices.
Required Skills
5–10 years of hands-on experience in ASIC RTL Design.Strong expertise in Microarchitecture, RTL design, and digital logic implementation.Solid experience with PCI Express (PCIe Gen4/Gen5/Gen6) architecture and protocol.Proficiency in Verilog/SystemVerilog with a strong understanding of synchronous digital design.Experience with Lint, CDC, RDC, Synthesis, and timing-aware RTL development.Good understanding of AMBA protocols (AXI/AHB/APB) and SoC integration.Familiarity with scripting using Python, Perl, Tcl, or Shell.Experience with Synopsys or Cadence RTL development and synthesis tools.Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.
Preferred Qualifications
Experience designing high-performance CPU, AI/ML, Networking, Storage, or Datacenter SoCs.Exposure to CXL, NVMe, DDR, or Ethernet protocols is an added advantage.Strong debugging, analytical, and problem-solving skills with the ability to work in cross-functional engineering teams.
LeadSoc Technologies Pvt Ltd
Location: Bengaluru, Karnataka, India
Work Mode: On-site
Industry: Semiconductor Manufacturing,Engineering Services,IT Services and IT Consulting
Job Description
ASIC RTL Design Engineer
Location: Bengaluru, India
Experience: 5–10 Years
Role Summary
We are looking for a highly skilled ASIC RTL Design Engineer to design and develop high-performance PCI Express (PCIe) IPs and SoC components. The ideal candidate will have strong expertise in microarchitecture definition, RTL design, and implementation of high-speed digital logic for next-generation semiconductor products.
Key Responsibilities
Design and implement RTL for PCI Express (PCIe) controllers, subsystems, and high-speed digital IPs.Translate architecture specifications into efficient microarchitecture and high-quality RTL.Develop scalable, high-performance, and low-power digital designs using Verilog/SystemVerilog.Perform functional analysis, logic optimization, lint, CDC, and synthesis-ready RTL development.Collaborate with Architecture, Verification, Physical Design, DFT, and Firmware teams throughout the development cycle.Support design reviews, debug functional issues, and resolve silicon bring-up challenges.Drive design quality through coding guidelines, documentation, and best engineering practices.
Required Skills
5–10 years of hands-on experience in ASIC RTL Design.Strong expertise in Microarchitecture, RTL design, and digital logic implementation.Solid experience with PCI Express (PCIe Gen4/Gen5/Gen6) architecture and protocol.Proficiency in Verilog/SystemVerilog with a strong understanding of synchronous digital design.Experience with Lint, CDC, RDC, Synthesis, and timing-aware RTL development.Good understanding of AMBA protocols (AXI/AHB/APB) and SoC integration.Familiarity with scripting using Python, Perl, Tcl, or Shell.Experience with Synopsys or Cadence RTL development and synthesis tools.Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.
Preferred Qualifications
Experience designing high-performance CPU, AI/ML, Networking, Storage, or Datacenter SoCs.Exposure to CXL, NVMe, DDR, or Ethernet protocols is an added advantage.Strong debugging, analytical, and problem-solving skills with the ability to work in cross-functional engineering teams.
More Info
Job Type:
Industry:
Employment Type:
Key Skills
PCI Express PCIe Gen4 Gen5 Gen6
Timing-aware RTL Development
ASIC RTL Design
RDC
Digital Logic Implementation
SoC Integration
Shell
About Company
Skills:
DDR, Pcie, Verilog, synthesis constraints, coherency memory subsystems, clock reset expertise, AMBA protocols, systemverilog, ECO flows, performance power analysis, Dft, ASIC RTL, cross-team collaboration, security blocks, low-power design, micro-architecture, SVA
Interesting Job Opportunity: Sykatiya Technologies - RTL Design Engineer - Verilog/ASICsykatiya technologies pvt ltd
Skills:
code coverage , Verilog, System Verilog, LINT, cdc, AXI protocol, Low power synthesis, Formality, SoC level Synthesis, UPF, Rtl Design, Synthesis, AMBA, Timing Analysis, RTL Coding, AHB, ip development, functional coverage, front-end design tools
Skills:
Uart, Spi, Verilog, I2c, LINT, cdc, MAS development, Sub-system design, SoC integration, ip design, Quality check flows, AMBA bus protocols, Axi, APB, RTL Coding, Medium complexity protocol, AHB, Microarchitecture