Shell, Perl, Verilog, Python, Tcl, LINT, cdc, PCI Express PCIe Gen4 Gen5 Gen6, systemverilog, Timing-aware RTL Development, ASIC RTL Design, Synthesis, RDC, Digital Logic Implementation, Microarchitecture, SoC Integration

Ecos, Tcl, Verilog, Python, DFT hooks, UPF, systemverilog, Ace, micro-architecture, low-power techniques, SVA, AHB, synthesis constraints, Timing Closure, APB, Axi, AMBA standard bus protocols

Low power microarchitecture techniques, High performance low latency high bandwidth design techniques, Verilog RTL logic design, Knowledge of logic design principles including timing and power implications, Experience with simulators and waveform debug tools, Area and power-efficient complex RTL design

Spi, Uart, Verilog, Arm, System Verilog, I2c, Gpio, USB standards, Synopsys, ASIC design flow, Interconnect fabrics, Arteris fabrics, RTL Coding, Cadence, Scripting in Perl, Peripheral interface IPs, QSPI, I3C, System Verilog assertions, NoC architecture, Third-party IP integration, Axi