Perl, Verilog, Python, Tcl, microarchitecture development, Synthesis, cdc, systemverilog, Rtl Design, RDC, EDA Tools, LINT, low-power methodologies, STA concepts

Area and power-efficient complex RTL design, High performance low latency high bandwidth design techniques, Low power microarchitecture techniques, Experience with simulators and waveform debug tools, Verilog RTL logic design, Knowledge of logic design principles including timing and power implications

Ecos, Tcl, Verilog, Python, DFT hooks, UPF, systemverilog, Ace, micro-architecture, low-power techniques, SVA, AHB, synthesis constraints, Timing Closure, APB, Axi, AMBA standard bus protocols

pipelining , Debugging, Perl, Verilog, Python, Tcl, Analytical Skills, Reset architecture, Clock domain crossing CDC, Micro-Architecture, Linting, Digital Design Fundamentals, systemverilog, FSM design, Synthesis, RTL quality checks, RTL Coding, Low-power design methodologies, ASIC SOC design, Timing Concepts

Spi, Uart, Verilog, Arm, System Verilog, I2c, Gpio, USB standards, Synopsys, ASIC design flow, Interconnect fabrics, Arteris fabrics, RTL Coding, Cadence, Scripting in Perl, Peripheral interface IPs, QSPI, I3C, System Verilog assertions, NoC architecture, Third-party IP integration, Axi