DDR, Pcie, Verilog, synthesis constraints, coherency memory subsystems, clock reset expertise, AMBA protocols, systemverilog, ECO flows, performance power analysis, Dft, ASIC RTL, cross-team collaboration, security blocks, low-power design, micro-architecture, SVA

code coverage , Verilog, System Verilog, LINT, cdc, AXI protocol, Low power synthesis, Formality, SoC level Synthesis, UPF, Rtl Design, Synthesis, AMBA, Timing Analysis, RTL Coding, AHB, ip development, functional coverage, front-end design tools

Uart, Spi, Verilog, I2c, LINT, cdc, MAS development, Sub-system design, SoC integration, ip design, Quality check flows, AMBA bus protocols, Axi, APB, RTL Coding, Medium complexity protocol, AHB, Microarchitecture