rtl development , Ecos, Spi, Constraints, I2c, Eeprom, Sta, memory integration, Digital Design, Uvm, Physical Design, Dft, formal verification, state machines, Verification, register maps, legacy code, Communication Protocols, Sram, EFuse, CDCs, Timing Constraints, RTL synthesis, digital concepts, I3C

Verilog, Cache, Soc Architecture, fabric coherence, memory compression, systemverilog, logic synthesis techniques, FPGA and emulation platforms, digital logic design principles, Synthesis, DRAM, FPGA design verification, assertion-based formal verification, RTL design concepts, Dft, low-power design techniques, power analysis

ASIC RTL Design, systemverilog, Micro-Architecture, Clock/Reset Design, Low-Power Design, UPF

Ecos, Tcl, Verilog, Python, DFT hooks, UPF, systemverilog, Ace, micro-architecture, low-power techniques, SVA, AHB, synthesis constraints, Timing Closure, APB, Axi, AMBA standard bus protocols

Low power microarchitecture techniques, High performance low latency high bandwidth design techniques, Verilog RTL logic design, Knowledge of logic design principles including timing and power implications, Experience with simulators and waveform debug tools, Area and power-efficient complex RTL design

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, ASIC Design, Veloce, formal verification

Uart, Spi, Verilog, I2c, LINT, cdc, MAS development, Sub-system design, SoC integration, ip design, Quality check flows, AMBA bus protocols, Axi, APB, RTL Coding, Medium complexity protocol, AHB, Microarchitecture

Spi, Uart, Verilog, Arm, System Verilog, I2c, Gpio, USB standards, Synopsys, ASIC design flow, Interconnect fabrics, Arteris fabrics, RTL Coding, Cadence, Scripting in Perl, Peripheral interface IPs, QSPI, I3C, System Verilog assertions, NoC architecture, Third-party IP integration, Axi