ASIC Engineer, SoC Architect
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Job Description
Description
We are seeking an experienced ASIC Engineer, SoC Architect to join our innovative team in India. The ideal candidate will have a strong background in ASIC design and SoC architecture, with a proven track record of delivering high-quality solutions. You will be responsible for designing, developing, and optimizing ASIC architectures, collaborating with cross-functional teams, and ensuring successful integration of new designs.
Responsibilities
- Design and develop ASIC architectures and SoC solutions for various applications.
- Collaborate with cross-functional teams to define specifications and requirements for new designs.
- Conduct performance analysis and optimization of existing designs.
- Create and maintain design documentation, including specifications, verification plans, and test cases.
- Participate in design reviews and provide constructive feedback.
- Support the integration and validation of new designs into existing systems.
Skills and Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Strong experience in ASIC design methodologies and tools (e.g., Cadence, Synopsys, Mentor Graphics).
- Proficiency in hardware description languages such as Verilog or VHDL.
- Experience with SoC architecture and design principles.
- Knowledge of digital design concepts and practices.
- Familiarity with RTL design, synthesis, and simulation processes.
- Experience with verification methodologies, including SystemVerilog and UVM.
- Strong problem-solving skills and attention to detail.
- Ability to work collaboratively in a team environment.
More Info
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About Company
Skills:
Verilog, low power design, systemverilog, Rtl Design, Asic, Architect
Skills:
physical design constraints, memory interconnect architecture, ASIC Design, Digital Design, low-power design techniques, architectural simulators, power estimation frameworks
Skills:
power optimization , Cpu, Noc, Tcl, Verilog, Networking, System Verilog, Python, Perl, LINT, Synthesis, High-Level Synthesis, Micro-architecture Development, Peripheral Subsystems, cdc, RTL Coding, Formal Verification Methodology, Timing Closure, Shell-scripting, power analysis
Skills:
static timing analysis, place-and-route, power analysis, Synthesis, multi-voltage domain design, Timing Closure, timing signoff, ASIC physical implementation, low-power implementation techniques
Skills:
Embedded Software, Rtl Design, GDSII flow, IP selection strategies, Verification