Verilog, low power design, systemverilog, Rtl Design, Asic, Architect

physical design constraints, memory interconnect architecture, ASIC Design, Digital Design, low-power design techniques, architectural simulators, power estimation frameworks

power optimization , Cpu, Noc, Tcl, Verilog, Networking, System Verilog, Python, Perl, LINT, Synthesis, High-Level Synthesis, Micro-architecture Development, Peripheral Subsystems, cdc, RTL Coding, Formal Verification Methodology, Timing Closure, Shell-scripting, power analysis

static timing analysis, place-and-route, power analysis, Synthesis, multi-voltage domain design, Timing Closure, timing signoff, ASIC physical implementation, low-power implementation techniques

Embedded Software, Rtl Design, GDSII flow, IP selection strategies, Verification

Soc Architecture, AMBA AXI CHI protocols, HW SW co-design, Memory subsystem architecture, PCIe CXL UCIe, Silicon bring-up and debugging, RTL and microarchitecture understanding, Performance analysis and simulation

Perl, Verilog, Python, Tcl, Cadence Palladium, Siemens Veloce, Synopsys ZeBu, systemverilog

Verilog, Design Verification, implement IP/SoC verification plans, systemverilog, C/C++, ASIC development cycles