ASIC Engineer, Physical Design
ASIC Engineer, Physical Design
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Job Description
Job description
Meta is looking for ASIC Engineer, Design Verification to join our dynamic team and embark on a rewarding career journey.
- Develop and implement ASIC design methodologies, including design, verification, and testing Collaborate with cross-functional teams to identify and understand requirements and develop solutions that meet business needs Develop and maintain design specifications, test plans, and documentation Participate in the full ASIC development cycle, including architecture, RTL design, verification, and synthesis Perform design optimization and analysis to ensure optimal performance and power efficiency Ensure compliance with industry standards and guidelines. Strong knowledge of ASIC design methodologies and tools. Excellent communication and interpersonal skills Strong analytical and problem-solving skills
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Key Skills
About Company
Skills:
Shell, Tcl Scripting, Python, Routing, Perl, Sta, CTS, Signoff, OCV, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, Signal Integrity, LVS, IR Drop, Physical Verification, MCMM, POCV, Setup Hold, RTL-to-GDSII Physical Design flow, floorplanning, Post-route Optimization, Placement Optimization, EM, Power Planning, Eco, Timing Closure, DRC, AOCV, Synopsys ICC2
Skills:
Verilog, System Verilog, Sta, Synthesis, Physical Verification, CTS, Synopsys physical design tools, DFT tools, Extraction, Timing Analysis, Place And Route
Skills:
ML optimization tools (DSO.ai), CTS and routing, Timing-driven placement, PPA Optimization, floorplanning, Hierarchical physical design, RTL-to-GDS implementation flow, Synopsys Fusion Compiler, Pin assignment, Timing budgeting
Skills:
Design Planning, Architecture and Microarchitecture, ASIC designs, Rtl Design, Physical Design Support, Synthesis and Optimization
Skills:
Verilog, Python, Tcl, Physical Verification, Sign-off Optimizations, High Performance Synthesis, Constraints Synthesis, Physical Design, Electrical Checks, systemverilog