Shell, Tcl Scripting, Python, Routing, Perl, Sta, CTS, Signoff, OCV, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, Signal Integrity, LVS, IR Drop, Physical Verification, MCMM, POCV, Setup Hold, RTL-to-GDSII Physical Design flow, floorplanning, Post-route Optimization, Placement Optimization, EM, Power Planning, Eco, Timing Closure, DRC, AOCV, Synopsys ICC2

Verilog, System Verilog, Sta, Synthesis, Physical Verification, CTS, Synopsys physical design tools, DFT tools, Extraction, Timing Analysis, Place And Route

ML optimization tools (DSO.ai), CTS and routing, Timing-driven placement, PPA Optimization, floorplanning, Hierarchical physical design, RTL-to-GDS implementation flow, Synopsys Fusion Compiler, Pin assignment, Timing budgeting

Design Planning, Architecture and Microarchitecture, ASIC designs, Rtl Design, Physical Design Support, Synthesis and Optimization

Verilog, Python, Tcl, Physical Verification, Sign-off Optimizations, High Performance Synthesis, Constraints Synthesis, Physical Design, Electrical Checks, systemverilog

Clp, Sta, Timing Constraints, RTL synthesis, LEC, low-power design concepts

Routing, Sta, CTS, floorplanning, EM, Ir, LVS, Physical Implementation, Synthesis, Physical Design, Placement, Si, DRC, RTL Netlist, Timing Closure, Tape-out, Power Domains, GDSII, Hierarchical Designs

congestion management , Python, Routing, Perl, Tcl, Sta, CTS, Advanced Floorplanning, Cadence Innovus, Physical Signoff, LVS, Fusion Compiler FC, UPF, MMMC, Power Distribution Network, Antenna, Multi-voltage design implementation, Placement Optimization, EM, Physical Verification, Ir, low power design, Physical Design, Timing Closure, ECO Implementation, DRC