ASIC Engineer, IP Design, Silicon

Responsibilities

• Define microarchitecture details, block diagram, data flow, pipelines, etc.
• Perform RTL development (SystemVerilog), debug functional/performance simulations.
• Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks.
• Participate in synthesis, timing/power estimation and FPGA/silicon bring-up.
• Communicate and work with multi-disciplined and multi-site teams.

Minimum qualifications:

• Bachelor's degree in Electrical/Computer Engineering or equivalent practical experience.
• 3 years of experience with Register-Transfer Level (RTL) design and integration using Verilog/System Verilog, microarchitecture and automation.
• Experience with RTL design using Verilog/System Verilog and microarchitecture.
• Experience with a scripting language like Python or Perl.

Preferred qualifications:

• Master's degree in Computer Science or Electrical Engineering.
• 6 years of industry experience with IP design.
• Experience with methodologies for low power estimation, timing closure, and synthesis.
• Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).