ASIC Engineer, Design Verification
- Posted a month ago
- Over 50 applicants have applied
Job Description
Job description
Meta is looking for ASIC Engineer, Design Verification to join our dynamic team and embark on a rewarding career journey.
- Develop and implement ASIC design methodologies, including design, verification, and testing Collaborate with cross-functional teams to identify and understand requirements and develop solutions that meet business needs Develop and maintain design specifications, test plans, and documentation Participate in the full ASIC development cycle, including architecture, RTL design, verification, and synthesis Perform design optimization and analysis to ensure optimal performance and power efficiency Ensure compliance with industry standards and guidelines. Strong knowledge of ASIC design methodologies and tools. Excellent communication and interpersonal skills Strong analytical and problem-solving skills
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Key Skills
About Company
Skills:
Tcl, Mercurial, Svn, DDR, Git, Pcie, Perl, Ethernet, Arm, Python, RISC-V, systemverilog, AMBA, Emulation, Design Verification infrastructure, System Verilog Assertions
Skills:
bandwidth management , Microprocessor Cores, SystemVerilog Assertions, Specman E, Verification and debug of IP subsystem SoCs, Industry-standard simulators, Revision control systems, Constrained-random verification environments, systemverilog, Packet processing, Regression systems, Congestion control, Hierarchical memory subsystems, Full verification life cycle, Vector processing units
Skills:
assertion based verification , Debugging Tools, Scripting Languages, systemverilog, Uvm, Testbench Development, FPGA Prototyping, coverage analysis, Design Simulation, Design Verification, Asic verification, SoC Verification
Skills:
Soc Architecture, System Verilog, scoreboarding, digital design fundamentals, verification concepts, simulation logs, Uvm, ASIC SoC functional verification, waveform tools, constrained-random stimulus, BUS Protocols, assertions, SVA, functional coverage
Skills:
UFS (Universal Flash Storage), C, C++, Vcs, Makefile, Perl, Verilog, Ethernet, System Verilog, System Verilog verification language, Uvm, System Verilog assertion and coverage code, Synopsys VIPs, Waveform analyzer, Asic Design Verification, ASIC flow, Processor based SoC level verification, AXI-AMBA protocol variants, PCIe Protocol