Tcl, Mercurial, Svn, DDR, Git, Pcie, Perl, Ethernet, Arm, Python, RISC-V, systemverilog, AMBA, Emulation, Design Verification infrastructure, System Verilog Assertions

bandwidth management , Microprocessor Cores, SystemVerilog Assertions, Specman E, Verification and debug of IP subsystem SoCs, Industry-standard simulators, Revision control systems, Constrained-random verification environments, systemverilog, Packet processing, Regression systems, Congestion control, Hierarchical memory subsystems, Full verification life cycle, Vector processing units

assertion based verification , Debugging Tools, Scripting Languages, systemverilog, Uvm, Testbench Development, FPGA Prototyping, coverage analysis, Design Simulation, Design Verification, Asic verification, SoC Verification

Soc Architecture, System Verilog, scoreboarding, digital design fundamentals, verification concepts, simulation logs, Uvm, ASIC SoC functional verification, waveform tools, constrained-random stimulus, BUS Protocols, assertions, SVA, functional coverage

UFS (Universal Flash Storage), C, C++, Vcs, Makefile, Perl, Verilog, Ethernet, System Verilog, System Verilog verification language, Uvm, System Verilog assertion and coverage code, Synopsys VIPs, Waveform analyzer, Asic Design Verification, ASIC flow, Processor based SoC level verification, AXI-AMBA protocol variants, PCIe Protocol

C, Pcie, Ethernet, SV, CXL, UCIe, Uvm, systemverilog

Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, AMBA, Test Bench, transaction level modeling, AXI4

shell scripting, Perl, Python, Tcl, mixed-signal design verification, Cadence Spectre simulation, Cadence Mixed-Signal Design Environment, SV UVM-based testbenches, VerilogAMS, behavioral modeling, systemverilog