ASIC Engineer, Design
ASIC Engineer, Design
META- Posted 10 hours ago
- Be among the first 10 applicants
Job Description
The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing with superior capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains.
ASIC Engineer, Design Responsibilities:
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
ASIC Engineer, Design Responsibilities:
- Architecture exploration
- Micro-architecture development
- Soft and hard IP identification, selection and integration
- Collaboration with verification and emulation teams in test plan development and debug
- Collaboration with implementation team to close the design on timing and power
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 8+ years of silicon development experience with experience of first-pass success in ASIC (Application-Specific Integrated Circuit) Development
- Experience in one of these skills: Micro-architecture and RTL development for complex control and data path IPs (Intellectual Properties), OR Experience in SoC (System on Chip) Micro-architecture, Design and Integration, OR Implementation, Power methodology development
- Experience with Verilog or System Verilog
- Lint, CDC (Clock Domain Crossing), Synthesis and Power Optimization
- Experience working across multiple projects
- Experience with scripting languages (TCL, Python, Perl, Shell-scripting)
- Experience in CPU, NOC (Network on Chip), Memory and Peripheral Subsystems
- Experience with Power Analysis and Optimization
- Experience in data path development
- Experience in HLS (High-Level Synthesis)
- Experience with Synthesis, Timing Closure and Formal Verification Methodology
- 15+ years of experience in silicon development
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
More Info
Job Type:
Industry:
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Key Skills
NOC (Network on Chip)
HLS (High-Level Synthesis)
Formal Verification Methodology
Shell-scripting
Memory and Peripheral Subsystems
Data path development
CDC (Clock Domain Crossing)
Implementation Power methodology development
Micro-architecture and RTL development
Power Analysis and Optimization
Cpu
About Company
Skills:
python, C, C++, PERL, Dft, Advantest 93000 tester, test pattern development, 93k test methods, APTG, test cell integration
Skills:
power integrity , assembly processes , DFA, Altium Designer, Stack-up Development, High-Speed Board Design, Autocad, Windchill PDMLink, Cable Assemblies, Signal Integrity, CAM350, Dfm, Pcb Design, Fabrication Workflows, IPC Standards, connectors, PCB Yield Optimization, Altium Allegro Scripting, Multi-layer PCB Layout, PTH Technologies, ECO ECN Processes, Cadence Allegro
Skills:
DSP & Signal Processing Algoriths, Fpga, Verilog, Vhdl, Xilinx, Sta, Matlab Simulink
Early Applicant
Skills:
Usb, Logic Design, Pcie, Verilog, System Verilog, Sta, Microarchitecture development, Rtl Design, Synthesis, VHDL, SDCC, Multi-clock designs, SoC design and integration
Skills:
C, Performance Modeling, Python, C++, Multi-bank SRAM architectures, AI ML data-movement patterns, Descriptor-based DMA gather scatter tensor tiling, Conflict Resolution, HBM controller architecture, HBM4e, HBM3E, Banking interleaving, Memory schedulers, DRAM, HBM3, Arbiters, Bandwidth efficiency optimization, Prefetching, RTL SystemVerilog design, DMA engines, Address mapping, HBM2E, UCIe NoC traffic interaction, Request reordering