python, C, C++, PERL, Dft, Advantest 93000 tester, test pattern development, 93k test methods, APTG, test cell integration

power integrity , assembly processes , DFA, Altium Designer, Stack-up Development, High-Speed Board Design, Autocad, Windchill PDMLink, Cable Assemblies, Signal Integrity, CAM350, Dfm, Pcb Design, Fabrication Workflows, IPC Standards, connectors, PCB Yield Optimization, Altium Allegro Scripting, Multi-layer PCB Layout, PTH Technologies, ECO ECN Processes, Cadence Allegro

DSP & Signal Processing Algoriths, Fpga, Verilog, Vhdl, Xilinx, Sta, Matlab Simulink

Usb, Logic Design, Pcie, Verilog, System Verilog, Sta, Microarchitecture development, Rtl Design, Synthesis, VHDL, SDCC, Multi-clock designs, SoC design and integration

C, Performance Modeling, Python, C++, Multi-bank SRAM architectures, AI ML data-movement patterns, Descriptor-based DMA gather scatter tensor tiling, Conflict Resolution, HBM controller architecture, HBM4e, HBM3E, Banking interleaving, Memory schedulers, DRAM, HBM3, Arbiters, Bandwidth efficiency optimization, Prefetching, RTL SystemVerilog design, DMA engines, Address mapping, HBM2E, UCIe NoC traffic interaction, Request reordering

Design-for-Test (DFT), Static Timing Analysis (STA), C, C++, Verilog, Xml, Low-power design principles, LINT, cdc, Logic Synthesis, 28nm and smaller silicon process technologies, systemverilog, Cadence tool flows, VHDL, Scan testability, formal verification

Timing Closure, Synthesis, primetime, Physical design implementation, floorplanning, Synopsys Fusion Compiler, Cadence Innovus, Tempus

Verilog, Design Verification, implement IP/SoC verification plans, systemverilog, C/C++, ASIC development cycles

Zephyr, Spi, Uart, Soc, Rtos, I2c, Python, Pcie, Embedded Linux, secure boot development, BootROM, lab instrumentation, protocol analyzers, embedded firmware systems, bare-metal environments, bootloaders, platform firmware development, Oscilloscopes, peripheral drivers