Perl, Python, Tcl, Emulation, systemverilog, System Verilog Assertions

Scripting Language, Linux Operating System, Logic Design, Agile development processes, Verification principles, DevOps design methodologies and tools, RTL design with Verilog or VHDL

routing, congestion analysis, IR drop, primetime, floorplanning, physical ECO implementation, physical optimization, Cadence Innovus, LVS, Power Planning, Physical Verification, antenna checks, Calibre, Physical Design, StarRC, ERC, Timing Closure, DRC, Placement, sign-off, RTL-to-GDSII, Synopsys ICC2

Vcs, Gdb, Shell, Perl, Verilog, Python, ASIC design flow, floor-planning, Timing Analysis, Rtl Design, Eco, Debussy, bring-up lab debug

PERL, Python, Tcl, Sta, RTL-GDS flows, Physical Verification, SNPS CAD Flow, SNPS CDNS-based tools

Java, Power Bi, AGILE, Prometheus, Grafana, Datadog, JIRA, New Relic, Jenkins, Typescript, Javascript, Confluence, Scaled Agile, Scrum, Splunk, Python, Azure DevOps, SDLC testing concepts, automated SW testing frameworks, GitLab CI, GitHub Actions, CI CD pipelines, release-automation tooling