bluebeam , Networking, Paga, Excel, Structure cabling, Technical drawings, Intrusion Alarm, ELV Systems, PIDS, Physical security system, Specifications, AV, Acad, Access Control, Cctv

Verilog, Rtl Design, RTL Coding, Micro-architecture, systemverilog, RTL Design Engineer

Perl, Tcl Scripting, Python, System Verilog, Synopsys Mentor VIPs, PCIe Gen3, random constraint-based testing, verification methodologies, performance power optimization, SMMU, CXL 1.1, Coresight architecture, assertion-based verification, Uvm, UPF, CHI protocols, Axi, formal verification, power-aware verification, coverage-driven testing, SVA

analog filters , test equipment , Circuit Design, SPICE Simulation, Signal Integrity, Transistor Modeling, Pcb Layout, RF Design, power management, Noise Analysis

Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, AMBA, Test Bench, transaction level modeling, AXI4

Verilog, Design Verification, implement IP/SoC verification plans, systemverilog, C/C++, ASIC development cycles