Zephyr, Spi, Uart, Scripting Language, Rtos, I2c, Python, Pcie, Embedded Linux, Oscilloscopes, Programming In C, secure boot development, BootROM bootloaders, lab instrumentation, protocol analyzers, embedded hardware platforms, platform firmware development, embedded system development, board bring-up, peripheral drivers, SoC block understanding

Perl, Python, Tcl, Calibre, ERC, DRC, Parasitic Extraction, EM, LVS, Cadence Virtuoso, IR analysis

Perl, Verilog, Python, Tcl, Cadence Palladium, Siemens Veloce, Synopsys ZeBu, systemverilog

Area and power-efficient complex RTL design, High performance low latency high bandwidth design techniques, Low power microarchitecture techniques, Experience with simulators and waveform debug tools, Verilog RTL logic design, Knowledge of logic design principles including timing and power implications

python, perl, Shell Scripts, low power design, RTL Coding, Synthesis, ASIC Design

Synthesis, multi-voltage design, floorplanning, SDC constraint development, MBIST, test specifications, Dfm, formal verification, Timing Closure, DRC, debug test coverage, Scan, ESD checks

C, Perl, Verilog, Shell scripting, Python, Tcl, SVA, UVM assertions, systemverilog

Python, Rtl Design, SoC methodology, AI-driven microarchitecture, simd, Low-power design techniques, FPGA prototyping, systemverilog, VLIW execution pipelines, ASIC components