Physical Design Lead

Lead Physical Design Engineer

Location: Bangalore / Hyderabad, India

Experience: 8+ Years

About the Role:

Cyient Semiconductors is looking for an experienced Lead Physical Design Engineer to drive the end-to-end physical implementation of complex ASIC/SoC designs. The ideal candidate should have strong hands-on expertise across the complete RTL-to-GDSII flow, with proven experience delivering successful tape-outs.

Key Responsibilities & Required Skills:

• 8+ years of hands-on experience in Physical Design for complex ASIC/SoC designs.
• Perform end-to-end RTL-to-GDSII physical design implementation for block-level and full-chip designs.
• Hands-on expertise in floorplanning, power planning, placement, Clock Tree Synthesis (CTS), routing, physical optimization, and sign-off.
• Strong experience in timing closure, IR drop, Electromigration (EM), congestion analysis, and physical ECO implementation.
• Hands-on experience with physical verification, including LVS, DRC, ERC, and antenna checks, using industry-standard sign-off tools.
• Proven tape-out experience on legacy and mature technology nodes (180nm, 130nm, 110nm, 90nm, 65nm, 55nm, 45nm, and 40nm), with exposure to advanced nodes such as 28nm, 16/14nm, 10nm, 7nm, 5nm, and below.
• Strong expertise with Cadence Innovus, Synopsys ICC2, PrimeTime, Calibre, StarRC, and other industry-standard EDA tools.
• Good understanding of timing constraints, sign-off methodologies, low-power design techniques, DFM, hierarchical implementation flows, and physical ECOs.
• Ability to collaborate effectively with RTL, STA, DFT, Package, and other cross-functional engineering teams to ensure successful tape-outs.
• Provide technical leadership by mentoring junior engineers, conducting design reviews, supporting project planning, and driving successful project execution.
• Strong analytical, debugging, communication, and stakeholder management skills.
• Candidates who can join immediately or within a short notice period will be preferred.

Educational Qualification:

• B.E./B.Tech or M.E./M.Tech in Electronics, VLSI Design, or related disciplines

If you're looking to work on challenging ASIC/SoC programs with a global team, we'd love to connect with you.

Interested Send your updated profile to [Confidential Information]

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