This position typically requires at least 2 to 3 years of related IP design or customer experience, but we may also consider candidates with less experience with the right academic background.
ASIC design experience with proven design background.
Experience in one or multiple steps on IP design or integration flow of ASIC / SoC design (such as simulation/verification, RTL synthesis, floor planning, physical design, timing closure, etc.) and silicon bring-up/characterization in a system environment.
Domain knowledge of at least one of the following protocols:
PCI Express
SERDES
Serial ATA
Good RTL and Gate Level simulation Debug skills
Familiarity with Front end implementation like Synthesis, Static Timing Analysis, Logical Equivalence Check
Preferred Experience
Technical knowledge with any Interface IP such as PCIe, USB, SATA, MIPI, HBM DDR, LPDDR Protocols, Specification, Design, and Implementation flows with Design Compiler, Fusion Compiler and PrimeTrime.
Excellent organization skills, excellent communication skills and ability to interact with customers
Proven track record in meeting tight schedules and handling multiple projects concurrently
