Analog Layout
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1.TSMC 16/12nm,7nm,5nm,3nm and below (other foundries are also fine like Intel, Samsung, GF). Preferably TSMC 7nm/5nm/3nm experience.
2.Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Analog blocks like Regulators/Charge pumps/Power Management etc..
3.Responsible for on-time delivery of block-level layouts of acceptable quality. TM should work independently.
4.Expertise in Cadence XL/EXL for Layout execution
5.Verification flows - LVS/DRC/DFM/Antenna check/EMIR experience.
6.Verification checks à Mentor Graphic's Caliber DRC/LVS is a must.
7.BE or MTech in Electronics/VLSI Engineering
8.Good communications skills as we work with cross-functional teams.
9.Share the profiles who have good hands-on experience in recent times on lowers nodes.
Good to have:
Qualifications:
B.Tech/MTech
HighPoints Technologies India Private Limited
Job ID: 152494617
Skills:
matching , Perl scripting, Dac, ADC, active and passive parasitic devices, Electro-migration, cross-talk, LVS, Latch-up, Comparator, Pll, Calibre, coupling, Differential Amplifier, advanced CMOS process, LDO, Analog Layout fundamentals, Critical Analog Layout design, Charge Pump, Temperature sensor, analog custom layout design, IR-drop, Bandgap Ref Generators, Current Mirrors, DRC, Cadence Virtuoso
Skills:
Design for manufacturability and testing considerations, Analog Layout, Power distribution challenges, Parasitic Extraction, Analog circuit design principles
Skills:
Dll, Analog Layout, Virtuoso-XL, Digital Place Route, Physical Verification, Calibre, SKILL Programming Language, ADC, virtuoso, LNA, Custom Layout, LDO, Assura, VGA, Hercules, Pll
Skills:
Electro migration, Analog Layout Engineer, Virtuoso schematic, parasitic analysis, virtuoso
Skills:
CMOS, VLE/VXL, Analog Layout, Cadence, DRC/LVS, Mask Design
