Analog Layout Engineer
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TSMC 16/12nm,7nm,5nm,3nm and below (other foundries are also fine like Intel, Samsung, GF). Preferably TSMC 5nm/3nm experience.
2. Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.
3. Verification flows - LVS/DRC/DFM/Antenna check/EMIR experience.
4. Responsible for on-time delivery of block-level layouts of acceptable quality.
5. Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must.
6. BE or MTech in Electronics/VLSI Engineering
7. Good communications skills as we work with cross-functional teams.
8. Share the profiles who have good hands-on experience in recent times on lowers nodes.
9. TM should work independently.
HighPoints Technologies India Private Limited
Job ID: 153907259
Skills:
EMIR, Mentor Graphic Caliber, Antenna check, DRC, LVS, Cadence VLE, TSMC 16 12nm 7nm 5nm 3nm and below, Dfm
Skills:
layout-dependent effects, LVS, PEX, analog mixed-signal IC design flows, device physics, layout methodology automation, deep-submicron advanced-node technologies, CMOS analog layout techniques, ERC, Cadence Virtuoso, DRC, custom analog IC layout, parasitics
Skills:
layout techniques for analog and mixed-signal circuits, Cadence Virtuoso Layout Editor VLE VXL, Mentor Graphics Calibre DRC LVS
Skills:
Electro migration, Analog Layout Engineer, Virtuoso schematic, parasitic analysis, virtuoso
Skills:
CMOS, VLE/VXL, Analog Layout, Cadence, DRC/LVS, Mask Design
