Knowledge of CMOS processes and issues in deep submicron process technologies.
CMOS circuit design and layout methodology & flow; basic understanding of analog/mixed signal circuitry, familiarity with basic ESD concepts is an advantage.
Familiarity with ASIC design flow.
Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus.
Ability to execute assigned circuit design tasks with best product quality and efficiency.
Good written and verbal communication skills in interactions with internal development teams.
