Analog Design, Sr Manager

Responsibilities:

- Manage and mentor a team of 8-10 senior analog designers focused on high-speed SerDes IP development across multiple projects

- Define architecture specifications and circuit implementation requirements for next-generation SerDes PHY IPs

- Ensure adherence to project schedules, quality metrics, power/area targets through effective team oversight

- Collaborate with cross-functional teams (digital design, physical design, CAD) to integrate analog IP components

- Partner with process engineering teams to enable robust analog IP across advanced FinFET nodes

- Continuously drive design methodology improvements and adoption of latest EDA tools/flows

- Develop and manage operational plan, including staffing, budgets and resource allocation

- Hire, develop and retain top analog engineering talent through active mentorship

Requirements:

- Bachelors degree in electrical engineering; advanced degree preferred

-8+ years of experience in analog/mixed-signal IC design with a strong background in SerDes architectures

- 2+ years of people management experience leading high-performance analog design teams

- Proven expertise in high-speed I/O design, architectures, circuits, and layout implementation

- Extensive knowledge of CDR, DFE, CTLE, EQ, decision feedback equalizer design techniques

- Hands-on experience with analog/mixed-signal design flows, tools (Cadence, Synopsys), modeling

- Understanding of FinFET transistor characteristics and design challenges at advanced nodes

- Strong project management skills with the ability to manage multiple priorities

- Excellent communication and people leadership abilities to motivate cross-functional teams