A layout technical expert taking chip top ownership of analog-on-top ASIC developments.
Hands-on technical contributor, able to take chip top ownership including tape-out procedures.
Hands-on in analog/mixed-signal layout methodologies, high-voltage design practices, and power IC architectures.
A team player, able to collaborate within a global layout team and cross-discipline stakeholders.
Gets drive & motivation from successfully taping out chips with the high quality layout.
Guide junior layout engineers, review their work, and enforce best practices.
Required experience:
10+ years of experience
Experience with nodes in the range of 40nm to 180nm is a must.
Experience with BCD technologies is a must. Experience with HV CMOS is a plus.
Strong knowledge of power management ICs and high-voltage layout constraints.
Experience with isolation technologies (transformer, capacitive, magnetic-based) is a plus.
Experience in die layout with package-level isolation and thermal requirements is a plus.
Experience with PMIC - buck/boost DC-DC converter, LDOs, high-voltage circuits.
Experience with integration of digital GDS/OA database in overall chip top-level.
Proven track record of owning chip top layout.
Aware of chip level ESD layout guidelines and best practices.
Aware of chip level LU related layout guidelines and best practices.
Proficient with Cadence Virtuoso and familiar with DRC/LVS/ERC tools (PVS or Calibre)
Must be able to independently go through required tape-out procedures and take corrective actions.
Must be able to take ownership of internal layout flows, continuously work on improvements and automation.
Must be able to understand foundry-specific constraints and convert this to direct actions and optimize internal tape-out checklists .
Familiarity with automation and Cadence skill is a plus
Daily tasks:
Key contributor to the successful realization of a project as part of the layout team.
Define ASIC floorplan and perform all tape-out verifications.
Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the design document, conform to standard layout practices, conform to foundry layout rules, including all remarks from review, the customer and back annotation.
Performs DRC and takes corrective actions if needed until DRC is error free
Performs LVS and takes corrective actions if needed until result is successful
Guide junior layout engineers, review their work, and enforce best practices.
Support the layout engineering team in handling complex layout issues.
Follow tape-out procedures for chip top sign-off and deliver final GDS to the foundry.
Must remain in contact with the foundry to efficiently find solutions to new challenges.
What we offer:
Opportunity to work on next generation PMIC & Power ASIC
Opportunity to improve company wide layout practices
Opportunity to work with global layout team and cross-discipline stakeholders
