monte carlo , Python, Functional Coverage, power management, Analog Mixed-Signal, Uvm, Assertions, systemverilog, Pvt, Mixed-Signal Debug, Verification Automation, RNM, AMS Verification, Verilog-AMS, Spice, AMS Simulation, PMIC

automation, Scripting, environment development, mixed signal verification fundamentals, Real model creation, verification planning, behavioral modelling of analog blocks, SoCs, model validation, verification of Power management IPs, PSL SV assertions development, Verilog-AMS, SV Verilog, VerilogA

Perl, Shell Scripts, Python, Tcl, Synopsys XA VCS, Verilog-AMS, Spectre AMS Designer, SystemVerilog RNM Real Number Modeling, Cadence Virtuoso, SystemVerilog UVM

Mentor, Uvm, firmware interaction, Synopsys, AMs, systemverilog, Cadence, Siemens, Calibration and link training flows, Register models, industry VIPs, Avery, SERDES

Verilog, Uvm, testbench creation, code coverage analysis, DFI protocols, logic simulation, systemverilog, Verilog-A, score boarding, AMS simulations, RTL debugging