C
AMS Verification
C
AMS Verification
ciliconchip2-4 Years
- Posted 15 hours ago
- Be among the first 10 applicants
Job Description
Core Skills: Verilog-AMS | Real Number Modeling (RNM) | SystemVerilog | UVM | SPICE Debug
Key Responsibilities
- Behavioral Modeling: Design and verify block-level models using Verilog-A/AMS, SystemVerilog, or RNM for top-level mixed-signal simulations.
- Testbench & Simulation: Build UVM-based testbenches, automated checkers, and run SPICE + digital co-simulations for AMS IPs (ADCs, DACs, LDOs, PLLs, SerDes, GPIOs).
- Debug & Closure: Analyze waveform mismatches (WaveView, SimVision), debug interface/corner-case failures, and drive functional coverage closure alongside design teams.
Requirements
- Experience: 2+ years of hands-on experience in AMS/Mixed-Signal design verification and debug.
- Languages & Methodologies: Proficient in SystemVerilog, UVM, Verilog-AMS, and SVA.
- Tools Exposure: Familiarity with EDA tools such as Cadence Virtuoso, DiscoveryAMS, Xcelium, or Synopsys XA / PrimeSim.
More Info
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Key Skills
About Company
Skills:
MATLAB, Python, VHDL-AMS, Verilog-AMS, Mentor Graphics, Synopsys, Cadence Virtuoso
Skills:
Real Number Modeling (RNM), Verification Coverage Analysis, Cadence Xcelium, coverage analysis, DAC Verification, Root-Cause Analysis, Mixed-Signal Waveform Analysis, Mixed-Signal Simulation, PLL Verification, ADC Verification, Regression Debugging, Mixed-Signal Interfaces, Cadence ADE Assembler, Analog Mixed-Signal Verification, Mixed-Signal Testbench Development, Cadence Mixed-Signal Design Environment, Analog Behavioral Modeling, Mixed-Signal Behavioral Models, Simulation Debugging, Analog Building Blocks, AMS Verification, Verilog-AMS, Cadence Virtuoso, AMS Verification Methodology
Skills:
simvision , Perl, Shell scripting, Python, Tcl, Xcelium, VIVA, VerilogAMS, Virtuoso ADE Assembler, SV RNM, System Verilog UVM, Regression flows
Skills:
Tcl Scripting, Unix Shell Scripting, Perl, Verilog, System Verilog, Python, Incisive, IMC, constrained randomization, behavioral modelling, metric driven, Uvm, ASIC design methodology, Spectre, System Verilog RNM, xCelium, vManager, assertions, VerilogAMS, mixed signal verification
Skills:
automation, Scripting, SoCs, Real model creation, mixed signal verification fundamentals, PSL SV assertions development, model validation, VerilogA, SV Verilog, environment development, verification planning, Verilog-AMS, verification of Power management IPs, behavioral modelling of analog blocks