MATLAB, Python, VHDL-AMS, Verilog-AMS, Mentor Graphics, Synopsys, Cadence Virtuoso

Real Number Modeling (RNM), Verification Coverage Analysis, Cadence Xcelium, coverage analysis, DAC Verification, Root-Cause Analysis, Mixed-Signal Waveform Analysis, Mixed-Signal Simulation, PLL Verification, ADC Verification, Regression Debugging, Mixed-Signal Interfaces, Cadence ADE Assembler, Analog Mixed-Signal Verification, Mixed-Signal Testbench Development, Cadence Mixed-Signal Design Environment, Analog Behavioral Modeling, Mixed-Signal Behavioral Models, Simulation Debugging, Analog Building Blocks, AMS Verification, Verilog-AMS, Cadence Virtuoso, AMS Verification Methodology

simvision , Perl, Shell scripting, Python, Tcl, Xcelium, VIVA, VerilogAMS, Virtuoso ADE Assembler, SV RNM, System Verilog UVM, Regression flows

Tcl Scripting, Unix Shell Scripting, Perl, Verilog, System Verilog, Python, Incisive, IMC, constrained randomization, behavioral modelling, metric driven, Uvm, ASIC design methodology, Spectre, System Verilog RNM, xCelium, vManager, assertions, VerilogAMS, mixed signal verification

automation, Scripting, SoCs, Real model creation, mixed signal verification fundamentals, PSL SV assertions development, model validation, VerilogA, SV Verilog, environment development, verification planning, Verilog-AMS, verification of Power management IPs, behavioral modelling of analog blocks

simvision , Cadence Xcelium, AMS SPICE, DMSO, verification planning, testcase creation, testbench development, Verisium, simulation debug, Cadence Virtuoso, Xps, Spectre UltraSim, analog mixed-signal simulation