SDF, automation, Ovm, Tcl Scripting, Verilog, Perl, GLS, Uvm, SV, RTL, Specman, test-bench development, HVL, sim debug, closure constraint randomization, functional and code coverages, assertions development, eRM methodology, formal verification

Bit Error Rate Tester (BERT), FPGA Design, Usb, Prototyping, C, C++, Labview, Pcie, Verilog, Ethernet, Python, Tcl, DP, SRIO, FPGA coding, DDRIO, Oscilloscopes, Network Analyzer, Pre-Silicon IP SoC Physical Layer Electrical Validation, Post-Silicon Physical Layer Electrical Validation, JESD204, RTL Coding, High speed SERDES protocol, PCB schematic and layout design

automation, Ovm, Tcl Scripting, Verilog, Perl, RTL, GLS, Uvm, SV, Specman, SDF sim debug, test-bench development, HVL, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification

static timing analysis, Unix Environment, Perl, Awk, Scripting Languages, Tcl, LINT, cdc, Simulation, Digital Design, architectural and micro architecture design, serial peripherals SPI, Logic Synthesis, formal verification, low power methodology and flow, Dft, RTL Coding, debugging EDA tool issues