Design Engineer II
- Posted 19 days ago
- Be among the first 20 applicants
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Minimum Qualifications
2-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation
Deep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc
Strong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc
Preferred Qualifications
Experience managing small teams (at least 2 members and above)
Experience leading the complete post silicon validation efforts for at least one full project
1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping
Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug.
Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL
Experience conducting hiring interviews and mentoring new hires
BE/BTech/ME/MTech or equivalent
We're doing work that matters. Help us solve what others can't.
Minimum Qualifications
2-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation
Deep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc
Strong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc
Preferred Qualifications
Experience managing small teams (at least 2 members and above)
Experience leading the complete post silicon validation efforts for at least one full project
1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping
Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug.
Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL
Experience conducting hiring interviews and mentoring new hires
BE/BTech/ME/MTech or equivalent
We're doing work that matters. Help us solve what others can't.
More Info
Key Skills
DDRIO
JESD204
SRIO
Post-Silicon Physical Layer Electrical Validation
PCB schematic and layout design
Pre-Silicon IP SoC Physical Layer Electrical Validation
FPGA coding
High speed SERDES protocol
About Company
Skills:
C, Fpga, C++, Python, Verilog RTL coding, Bit Error Rate Testers, Ethernet PCIe UCIe standards and Protocols, Physical Layer and Protocol layer experience, Debug skills, Analyzers, Oscilloscopes, Protocol Exercisers, Electrical and Protocol Interoperability and Compliance test suites, ESD Latchup HTOL tests
Skills:
Fpga, C, Pcie, Ethernet, Python, Test result analysis, Verilog RTL coding, ESD Latchup HTOL tests, Analyzers, Oscilloscopes, Peripheral chips, High speed SERDES, High speed interface design techniques, UCIe, Debug skills, Lab automation scripts, Schematic and layout level, Bit Error Rate Testers, CXL, Electrical and Protocol Interoperability and Compliance test suites, Protocol Exercisers, Post-Silicon PHY Systems Interop and Compliance testing, Signal and Power integrity checks
Skills:
Fpga, C, Pcie, Ethernet, Python, Test result analysis, Calibration compliance lab suites, Verilog RTL coding, ESD Latchup HTOL tests, Analyzers, Oscilloscopes, High speed SERDES, UCIe, Debug skills, Lab automation scripts, Bit Error Rate Testers, CXL, Electrical and Protocol Interoperability and Compliance test suites, Protocol Exercisers, Signal and Power integrity checks, Post-Silicon PHY Systems Interop and Compliance testing
Skills:
C, Perl, Computer Architecture, Ruby, Python, Assembly start up code, Makefiles, Stimulus generation, Uvm, Testbenches, Pre-silicon verification, Formal verification methods, Linker scripts, Post-silicon FPGA validation
Skills:
Verilog, Bash, Python, Tcl, systemverilog