transistor-level layout matching, parasitic effects, Cadence Virtuoso Layout Suite, Synopsys Custom Compiler, physical verification closure, LVS, Calibre DRC LVS, Physical Verification, antenna checks, layout debugging, symmetry, FinFET technology nodes, analog mixed-signal IPs, ERC, DRC, Parasitic Extraction, full-custom layout for IO circuits

Physical Verification, Physical Layout Implementation, Samsung Process Technologies, DRC, LVS, Advanced Semiconductor Technology Nodes, Memory Layout Design

Calibre, signal integrity practices, high-speed design, virtuoso, SiP tool suite, Cadence APD, Constraint Manager, PCB layout tools, Valor

CMOS fundamentals, PEX, post-layout verification, Siemens EDA tools, LVS, semiconductor device physics, Analog Mixed-Signal IC Design, Analog Layout, ERC, DRC, IC design layout methodologies, Cadence Virtuoso

shielding , Pvs, Crosstalk, LVS, MUX Control Blocks, Latch-up, Sense Amplifiers, Assura, Memory Compiler, Esd, Critical Signal Routing, Antenna, DRAM, Memory Periphery Circuits, Cadence VLE, Calibre DRC, EM, IR-drop, Sram, Custom Memory Layouts, LVS DRC debugging, Bitcell Arrays, Memory Layout Design, Rom, Flash Memory Layout Design, Wordline Decoders, Rf, ERC

Automation Scripting, AI-assisted workflows, FinFET, LVS, Dfm, Physical Verification, CMOS, bicmos, EMIR, SiGe, ERC, EDA Tools, DRC, RF layouts, Cadence Virtuoso

Memory Architecture, Floor Planning, Antenna Electro Migration, ERC, Mentor Graphics Calibre, DRC, RC requirements, LVS, Cadence Virtuoso, ICV