Shell, Perl, Python, Tcl, Test Cases, Cadence Xcelium, Mentor QuestaSim, Synopsys VCS, Constrained Random Verification, Functional Verification, PCI Express PCIe protocol, ASIC SoC Design Verification, Functional Coverage Models, Verification Plans, Waveform analysis, Assertion-Based Verification SVA, Simulation Tools, SystemVerilog UVM, Testbenches, Assertions

Ovm, Debugging, Test Planning, CHI, SoC design verification, AMBA protocols, Uvm, UVM-based test benches, system simulation tools, Axi, APB, emulation models, AHB

Object Oriented Programming, Shell, Perl, Python, Make file, Power aware verification, Gate-Level Simulation, Assembly level testcases, System Verilog UVM, Mentor, Cadence, UPF, Assertions, System Verilog Testbench Architecture, Processor Architecture, Processor Verification, TCI, Synopsys, formal verification, Digital Design

Verilog, System Verilog, C, Jtag, SOC RTL Design Verification, Uvm

Usb, Tcl, Ethernet, Python, Perl, Pcie, DDR, systemverilog, Uvm, coverage-driven verification, AMBA, digital design RTL understanding, SVA, MIPI

arm architecture , Ovm, CPU design tools and methodologies, Uvm, VMM, Asic Design Verification

Perl, Verilog, Python, Xcelium, Cadence Incisive, complex testbenches, Uvm, systemverilog, Synopsys VCS, RTL design concepts, formal verification, VHDL, verification environments, Modelsim

code coverage , Design Verification Engineer, Low Power Verification Engineer, Power-Aware Verification Engineer, ASIC Design Verification Engineer, systemverilog, Uvm, Constrained Random Verification, Gate-Level Simulation, Timing Simulation, PAGLS, Testbench Development, VIP Integration, Coverage Closure

Scripting Languages, Sed, Perl, Awk, ASIC design flow, C Assertions coding, ARM based SOC software framework, SV-UVM, UVM assertion based coverage driven verification, constraint random test generation, multi-core multi-layer APIs, functional coverage, ARM processor based SoC architecture, ASIC verification methodologies