hardware security , Ras, Ethernet Networking, Pcie, Arm Processor, Soc Architecture, Design Verification, SoC Debug, Functional Safety, NOC Subsystems, CMN mesh, Micro-architecture, CPU X86, SoC Design Integration, Rtl Design

Clock Domain Crossing (CDC), PrimeTime Static Timing Analysis (STA), Design for Test (DFT) analysis, congestion analysis, area optimization, Timing Analysis, gate-level netlist generation, Power Estimation, RTL-to-gate-level equivalence checking, regression checks, Logic Synthesis, linting, formal verification, Timing Constraints, RTL Coding, Timing Closure, automation scripts, front-end design tools

Rtl Design, RTL quality checks, Micro-architecture design, SOC integration

Verilog, Tcl, Python, Perl, UPF, LEC Logic equivalence check, LINT, VSI, SV, IPXACT, Vc static or equivalent other tools, RTL Coding, SoC IP level Integration, Reset domain crossing RDC, Formality, Timing concepts SDC, 0in, conformal LEC tool, VC spyglass, Clock domain crossing CDC

Unix, Shell, Linux, Python, Skill, Rtl Design, SoC Integration

Verilog, Uvm, Synopsys VCS, VHDL, RTL design methodologies, Modelsim, Cadence Incisive