Heterogeneous multicore shared memory, CPU simulator development, MMU, 64-bit DSP processor, Verification, Digital IC Design, 64-bit vector processor ISA architecture development, Cache systems

routing, Sta, floorplanning, IR drops, LVS, Physical Verification, timing convergence, Electromigration, RTL synthesis, design ECO, DRC, GDS implementation

Perl, Python, Tcl, UPF, ATPG, Parasitics, IR-drop Analysis, Low-power Implementation, Physical Verification, DFT Insertion, Physical Design, Timing Closure, schematic capture, Layout Matching

Python, Tcl, EDA Tools, PrimeClosure, floorplanning, CTS, Innovus, Aspen, Sta, ICC2, IO Timing ECO, Physical Design, Tempus, Postroute Optimization, Seahawk, Placement, Timing Closure, DRC closure, EMIR drop

redhawk , Synopsys ICC2, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Tempus, Voltus

Static Timing Analysis (STA) tools, Cadence Innovus Implementation System, Digital timing concepts, Physical verification tools, Synopsys Fusion Compiler

routing, Static Timing Analysis, placement guidelines, chip finishing, LVS, clock-tree synthesis, Dfm, Synthesis, Physical Verification, place route flow, DRC, timing optimizations, Floorplan design, Low Power implementation, congestion reduction techniques, hierarchical designs, parasitic extractions, sign-off requirements