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Physical design Engineer
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Physical design Engineer
NXP Semiconductors India Private LimitedEarly Applicant
- Posted 11 days ago
- Be among the first 50 applicants
Job Description
Generic Job Description (not Job Level specific): The Digital Physical Design Engineer / Architect is responsible for a physical implementation of IP, Subsystem or IC design. The individual is responsible from RTL synthesis to GDS implementation and optimization of design including floorplanning, routing, timing convergence (STA) including related design ECO and physical verification for fulfilling all Technology & reliability related rules, such as DRC/LVS/Electromigration/IR drops. The individual contributes to problem solving related to physical design. Contributes to define best Physical design strategy per technology node.#LI-9415
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Key Skills
IR drops
timing convergence
RTL synthesis
design ECO
DRC
GDS implementation
About Company
Skills:
clock tree synthesis (CTS), timing constraints (SDC), Static Timing Analysis (STA), routing, setup hold analysis, floorplanning, RTL-to-GDSII physical design flow, Digital Design, VLSI fundamentals, CMOS concepts, Timing Closure, Placement
Skills:
Perl, Python, Tcl, UPF, ATPG, Parasitics, IR-drop Analysis, Low-power Implementation, Physical Verification, DFT Insertion, Physical Design, Timing Closure, schematic capture, Layout Matching
Skills:
Python, Tcl, EDA Tools, PrimeClosure, floorplanning, CTS, Innovus, Aspen, Sta, ICC2, IO Timing ECO, Physical Design, Tempus, Postroute Optimization, Seahawk, Placement, Timing Closure, DRC closure, EMIR drop
Skills:
redhawk , Synopsys ICC2, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Tempus, Voltus
Skills:
Voltus, Cadence Tools, PERC, Latup-Up, Power Grid planning, Tempus, LVS, Signal and Power bump planning, Innovus, Pegasus PVS, Esd, DRC, EMIR SigEM, Backend Signoff flows, Cell EM