Fpga, Perl, Python, test bench infrastructure, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog

python, perl, Specman E, Cadence JasperGold, test bench qualification, SystemVerilog UVM, Certitude, regression and coverage analysis tools

Mac, Pcie, Switch, 1G Ethernet, UFS, SV, XUSB, High Speed IO verification, Uvm, verification tools for simulation and debug

C, C++, Makefile, Windows, Shell, Linux, Verilog, System Verilog, Python, IP level ASIC verification, SystemVerilog language, acceleration HLS tools process, UVM testbenches, automating workflows in a distributed compute environment, UVM concepts, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, UVM based verification frameworks, testbenches processes and flows

C++, DDR, Arm Assembly, Pcie, X86, Ethernet, System Verilog, Python, Tcl, AArch64, CHI, Ace, Palladium, FPGA Prototyping, AMBA, Mentor Veloce, Zebu, LPDDR, AXI4

C, C++, low power design verification techniques, coverage planning, power management verification, SystemVerilog testbench development, coverage closure, Asic Design Verification, GLS power aware verification, ACPI standards, post-si verification, clocking reset power-up sequences, functional coverage

Real Number Modeling (RNM), Python, Tcl, Verification automation, Regression management, Verification flows, Cadence Virtuoso AMS Designer, Uvm, systemverilog, SystemVerilog-AMS, AMS simulation tools, Analog behavioral modeling, Functional coverage debugging

memory controllers , Uart, Spi, Can, Jtag, I2c, C Programming, Ocp, Flash, System Verilog, SWD, Ace, ARM debug subsystem, Microprocessor architecture, Sram, Uvm, ARM Cores, Rom, AMBA, Axi, MIPI CSI2, AHB