Formal Verification Engineer

Formal Verification Engineer-

Targets

High quality silicon with no functional bugs by performing high quality pre-silicon verification

Tasks

• Develop Specman E and SystemVerilog UVM compliant verification environments
• Formal verification of IPs (e.g. DMA, NVM FSMs)
• Creation of verification plans and execution of coverage closure
• Provide relevant reports to show progress
• Run regressions / help set up automatic regressions and debug failures / drive debugging
• Run verification environments quality checks with Certitude and improve environment to reach ASIL-D level for verification environment

Skillset

• Proven working experience within the semiconductor industry in constraint random functional and formal verification
• Expertise in hardware verification using SystemVerilog UVM
• Expertise in formal verification using Cadence JasperGold
• Knowledge of using regression and coverage analysis tools as well as knowledge of test bench qualification
• Working experience in international and cross-functional technical teams within a multi-cultural environment
• Excellent English communication skills

Deliverables

• Testcases ready for regression
• Plans for reaching defined verification KPIs
• Qualified verification environment using formal verification tools
• Intermediate reports and debug of failing test cases, coverage gap analysis
• Verification sign-off report fulfilling defined KPIs (e.g. 100% coverage)

Tools

Cadence JasperGOLD, Xcelium, Vmanager Enterprise edition, System Verilog, VHDL, basic knowledge of scripting languages – perl / python, Certitude