Shell, System Verilog, Python, Vcs, Perl, Gdb, RTL, Uvm, Debussy, Asic verification

code coverage , Usb, Hdl Languages, DDR, Shell, Pcie, Perl, Ethernet, Python, Debugging, verification test plans, constrained-random test cases, UCIe, Uvm, systemverilog, CXL, simulation test benches

Tcl, Mercurial, Svn, DDR, Git, Pcie, Perl, Ethernet, Arm, Python, RISC-V, systemverilog, AMBA, Emulation, Design Verification infrastructure, System Verilog Assertions

Rtl Design, Synthesis, ASIC development cycle, formal verification, ASIC design methodologies, architecture, Verification

Asic, Rtl Design, Analytical Skill, Problem Solving Skills, formal verification

Perl, Vcs, Tcl, NC, Uvm, systemverilog