Verilog, System Verilog, Assertion Checker Development, Coverage Closure, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, IP SOC Verification, Design Verification Failure Debugging, Concepts in Digital Design

Verilog, systemverilog, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, VMM, random stimulus

Perl, Ruby, System Verilog, Asic verification, Rtl Design, make, Uvm, formal verification, TestBench Development

Verilog, Matlab, Python, FPGA-based emulation, DSP concepts

Perl, Ruby, System Verilog, make, Uvm

Tcl, Shell scripting, Python, Perl, Debugging, Uvm, systemverilog, Mixed-Signal Verification

Verilog, cdc, VHDL, RDC, Test plan creation and execution, Formal verification methodologies, Uvm, Constrained random verification techniques, systemverilog

DDR, Pcie, Perl, Vcs, Python, Tcl, Uvm, Axi, Verdi, APB, Questa, systemverilog