Design Verification Engineer
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Job Title: Design Verification Engineer
Exp Level:2+yrs
Location: Bangalore/Hyderabad
Job Description:
Responsible for ensuring functional correctness of ASIC/SoC designs.
Key Task: Develop and execute verification plans for complex digital designs.
Methodology: Use UVM/SystemVerilog to create testbenches, write test cases, and debug failures.
Coverage: Achieve functional and code coverage targets through constrained random and directed testing.
Collaboration: Work with RTL designers to identify and resolve design bugs.
Tools: Leverage industry-standard tools (VCS, Questa, Verdi) for simulation and debug.
Protocols: Verify IP/SoC-level designs for common protocols (AXI, APB, PCIe, DDR, etc.).
Automation: Develop scripts (Python/Perl/TCL) to improve verification efficiency.
Documentation: Maintain verification reports and review results with stakeholders.
Compliance: Ensure adherence to project timelines and quality standards.
Interested can share CV to [Confidential Information]
Job ID: 144816385
Skills:
Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers
Skills:
Test Planning, Ovm, Debugging, CHI, Uvm, system simulation tools, AHB, UVM-based test benches, SoC design verification, APB, Axi, emulation models, AMBA protocols
Skills:
Shell, Python, Perl, Scripting Languages, DACs, Uvm, SV, Dms, behavioral modeling, Signal Processing, digital RTL, ADC, Synopsys VCS, Analog Mixed Signal, DV, full chip verification, Cadence Virtuoso, verification plan, Oscillators, Pll, Debug
Skills:
Verilog, systemverilog, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, VMM, random stimulus
Skills:
wireless protocols , modem, System Verilog, Wifi Standards, constraint random tests, assertion coverage-based verification methodology, debugging RTL TB issues using Verdi, Uvm, formal static verification methodologies
