Routing, Full-chip dependencies, FCFP, Defs, Feed planning, Timing Closure, Tile floorplanning, PhyV, Placement, FCT, Timing, Shapes, Pins, EM-IR

Routing, power analysis, Synthesis, EMIR, floorplanning, Placement, Physical Design Implementation, Power Planning

Mentor-Calibre, Physical Verification, pegasus, Cadence Innovus, EM IR drop analysis, Static Dynamic IR analysis, EDA tool automation, Voltus

power optimization , Eda, Tcl Scripting, Python, power analysis, Sta, Agentic AI methodologies, DVFS, LEC, AI-driven optimization, Place And Route, UPF, Physical Verification, Timing Power closure, Asic Physical Design, Physical Verification, full chip and block level floor-planning, Eco, multi-Vt power domains, RTL to GDS Flow, CPF, LLM-assisted debugging, autonomous agents