clocking , Ras, Python Scripting, Gpio, System Verilog, Verification debug tools, Fuse, Uvm, power management, Xeon Global flows, Reset flows, Security flows, Pre silicon validation

Linux, Verilog, Unix Scripting, Cadence Palladium, Siemens Veloce, RTL Compilation, Synopsys ZeBu, Debugging Issue Analysis, Pre-Silicon Validation, systemverilog, Emulation Model Build Compilation

Unix, Linux, Perl, Shell scripting, Python, Functional Coverage, Assertions SVA, Emulation Platforms, Palladium, Uvm, RTL Debug, systemverilog, ZeBu, Veloce

Debugging, Software testing acceleration, Emulation, Zebu, Veloce, Hardware design validation, Palladium

lauterbach , Spi, C, Systemc, Usb, Shell, Tcl, Verilog, Jtag, Python, Pcie, Perl, DDR, Axi, Coresight, LPDDR, RTL, UltraSoC, Cadence Palladium, systemverilog, VHDL, Cadence Palladium XP, ZeBu

FPGA Design, Python Scripting, Soc Architecture, Test Automation, systemverilog, Verification Methodology, Hardware Debugging, Signal Integrity, Performance Analysis, Emulation Tools

DDR, Pcie, Ethernet, Building complex SOC emulation models, Emulation model development, Memory technologies interfaces, Transactor integration, SOC inter-connect buses, Palladium, Processor Architecture, SOC components, IO protocols, Model bring-up activities, HBM, Zebu, Veloce, CXL

Tcl, Verilog, System Verilog, C, Gdb, Python, Veloce, Zebu, waveform debuggers, Palladium