Perl, Python, Tcl, primetime, constraint development, Fusion Compiler, low-power design methodologies, Timing Analysis, Cadence Genus, UPF-based flows, RTL synthesis, Synopsys Design Compiler, Timing Closure

conformal lec , Perl, Shell script, Tcl, Pre-STA timing analysis, DFT Insertion, Fusion Compiler, Conformal Low Power, Formality, Tempus, VCLP tool, Functional ECO flow, Logic equivalence check, primetime, Physical Synthesis, UPF Low power concepts, Genus, Low power check

static timing analysis, shell scripting, Perl, Verilog, Tcl, ASIC design flow, Synthesis, VHDL, Synopsys DC PT tools